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| 1994 8-bit single-chip microcomputer document no. ic-3233a (o. d. no. ic-8702a) date published march 1995 p printed in japan m pd78cp18(a) mos integrated circuit data sheet the information in this document is subject to change without notice. the mark h shows major revised points. description the m pd78cp18(a) is a version of the m pd78c18(a) in which the internal mask rom is replaced by one-time prom. the one-time prom version can be programmed once only by users, and is ideally suited for small-scall of many differnt products, and rapid development and time-to-market of a new product. the detailed functions are descrived in the following user's manual. read this manual before starting design work. 87ad series m pd78c18 user's manual: ieu-1314 features high reliability compared to the m pd78cp18 compatible with the m pd78c11a(a), 78c12a(a), 78c14(a), 78c18(a) internal prom: 32768 w 8 ? internal prom capacity can be changed by software to conform to the m pd78c11a(a), 78c12a(a), 78c14(a), 78c18(a). prom programming characteristics: m pd27c256a compatible power supply voltage range: 5 v 10 % supports qtop ? microcomputer remark qtop microcomputer is the generic name of nec's single-chip microcomputers for which nec provides total service including writing, marking, screening, and inspection. ordering information part number package internal rom m pd78cp18gf(a)-3be 64-pin plastic qfp (14 20 mm) one-time prom m pd78cp18gq(a)-36 64-pin plastic quip one-time prom quality grade part number quality grade m pd78cp18gf(a)-3be special m pd78cp18gq(a)-36 special please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. h 1993
2 m pd78cp18(a) pin configuration (top view) m pd78cp18gq(a)-36 1 a0/pa0 2 a1/pa1 3 a2/pa2 4 a3/pa3 5 a4/pa4 6 a5/pa5 7 a6/pa6 8 a7/pa7 9 pb0 10 pb1 11 pb2 12 pb3 13 pb4 14 pb5 15 ce/pb6 16 oe/pb7 17 pc0/t x d 18 pc1/r x d 19 pc2/sck 20 pc3/int2 21 pc4/to 22 pc5/ci 23 pc6/co0 24 pc7/co1 25 a9/nmi 26 int1 27 mode1 28 reset 29 mode0 30 x2 31 x1 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v dd stop/v pp pd7/o7 pd6/o6 pd5/o5 pd4/o4 pd3/o3 pd2/o2 pd1/o1 pd0/o0 pf7 pf6/a14 pf5/a13 pf4/a12 pf3/a11 pf2/a10 pf1 pf0/a8 ale wr rd av dd v aref an7 an6 an5 an4 an3 an2 an1 an0 av ss 3 m pd78cp18(a) m pd78cp18gf(a)-3be an4 an3 an2 an1 an0 av ss v ss x1 x2 mode0 reset mode1 int1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 a0/pa0 a1/pa1 o3/pd3 o4/pd4 o5/pd5 o6/pd6 o7/pd7 v pp/ stop v dd a2/pa2 a3/pa3 a4/pa4 a5/pa5 45678910111213141516171819 pf3/a11 pf2/a10 pf1 pf0/a8 ale wr rd av dd v aref an7 an6 an5 pf7 pf6/a14 pf5/a13 pf4/a12 51 50 49 123 pb1 pb2 pb3 pb4 pb5 ce/pb6 oe/pb7 pc0/t x d pc1/r x d pc2/sck pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 a9/nm1 a6/pa6 a7/pa7 pb0 pd2/o2 pd1/o1 pd0/o0 4 m pd78cp18(a) serial i/o x1 alu (8/16) pc0/t x d x2 pc1/r x d pc2/sck osc int. control a9/nmi int1 8 8 4 8 timer timer/event counter 8 8 8 pc3/int2/ti pc4/to pc5/ci pc6/co0 pc7/co1 a/d converter v aref av dd av ss 8 latch inc/dec pc sp ea ea' va bc de hl v' a' b' c' d' e' h' l' buffer 10 16 15 prom (32-kbyte) data memory (1-kbyte) 8/16 inst. reg latch latch 16 16 internal data bus 16 16 16 6 inst. decoder 8 8 standby control system control read/write control reset v ss v dd v pp/ stop mode0 mode1 ale wr rd port f 8 8 5 port d 8 8 8 port c 8 pc7 to pc0 8 port b 6 pb5 to pb0 8 port a 8 pa7/a7 to pa0/a0 8 16 an7 to an0 psw pd7/o7/ad7 to pd0/o0/ad0 pf7/ab15 main g.r alt g.r 88 pf6/a14/ab14 to pf2/a10/ab10 pf1/ab9 pf0/a8/ab8 oe/pb7 ce/pb6 note block diagram note can be used only when rae bit of mm register is 1. external memory is needed in case of 0. 5 m pd78cp18(a) differences between the m pd78cp18(a) and m pd78cp18 m pd78cp18 m pd78cp18(a) standard special input leakage current an7 to an0; 10 m a (max.) ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic quip ? 64-pin plastic qfp (14 20 mm) ? 64-pin ceramic shrink dip with window (750 mil) ? 64-pin ceramic wqfn input leakage current an7 to an0: 1 m a (max.) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic quip quality grade electrical specifications package product name item 6 m pd78cp18(a) contents 1. list of port functions .......................................................................................................................7 1.1 port functions ............................................................................................................................... ................7 1.2 non-port functions (in normal operation) ..................................................................................... 8 1.3 non-port functions (during prom write/verify and read) .....................................................10 1.4 handling of unused pins .........................................................................................................................10 2. memory configuration ....................................................................................................................11 3. memory extension .............................................................................................................................16 3.1 mode pins ............................................................................................................................... .........................16 3.2 memory mapping register (mm) ............................................................................................................17 4. prom programming ...........................................................................................................................20 4.1 prom programming operating modes ...............................................................................................21 4.2 prom writing procedure .........................................................................................................................22 4.3 prom reading procedure .........................................................................................................................23 5. screening of one-time prom versions ......................................................................................24 6. electrical specifications ................................................................................................................25 7. characteristic curves (reference value) ..............................................................................39 8. package drawings .............................................................................................................................42 9. recommended soldering conditions ........................................................................................44 10. differences between the m pd78cp18(a) and m pd78c18(a) .....................................................45 appendix. development tools ..........................................................................................................46 7 m pd78cp18(a) 1. list of port functions 1.1 port functions pa7 to pa0 (port a) input/output pb7 to pb0 (port b) 8-bit input-output port, which can specify input/output bit-wise. function pin name i/o pc7 to pc0 (port c) pd7 to pd0 (port d) pf7 to pf0 (port f) 8-bit input-output port, which can specify input/output in byte units. 8-bit input-output port, which can specify input/output bit-wise. remark these port pins have alternate function pins as shown in 1.2 non-port functions (in normal operation) and 1.3 non-port functions (during prom write/verify and read) . 8 m pd78cp18(a) 1.2 non-port functions (in normal operation) pin name i/o output t x d (transmit data) r x d (receive data) sck (serial clock) int2 (interrupt request) input/output serial data output pin serial data input pin function pc1 pc0 pc2 input pc3 edge trigger (falling edge) maskable interrupt input pin timer external clock input pin ti (timer input) zero-cross to (timer output) ci (counter input) ac input zero-cross detection pin during timer count time, square wave with one internal clock cycle as one half cycle is output. timer/event counter external pulse input pin input input input output pc5 pc4 co0 and co1 (counter output 0, 1) ad7 to ad0 (address/data bus 7 to 0) ab15 to ab8 (address bus 15 to 8) serial clock input/output pin. output when internal clock is used, input when external clock is used. output pc6 and pc7 square wave output programmable by timer/event counter. input/output pd7 to pd0 multiplexed address/data bus when external memory is used output pf7 to pf0 address bus when external memory is used output strobe signal which is output for write operation of external memory. it becomes high in any cycle other than the data write machine cycle of external memory. when reset signal is either low or in the hardware stop mode, this signal becomes high-impedance. output strobe signal which is output for read operation of external memory. it becomes high in any cycle other than the data read machine cycle of external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high-impedance. rd (read strobe) wr (write strobe) output ale (address latch enable) strobe signal to latch externally the lower address information which is output to pd7 to pd0 pins to access external memory. when reset signal is either low or in the hardware stop mode, this signal becomes high- impedance. mode0 mode1 (mode) set mode0 pin to 0 (low level), and mode1 pin to 1 (high level) note non-maskable interrupt input pin of the edge trigger (falling edge) nmi (non-maskable interrupt) input note pull-up. pull-up resister r is 4 [k w ] r 0.4 t cyc [k w ] (t cyc is ns unit). alternate function pin input input input/output 9 m pd78cp18(a) x1, x2 (crystal) reset (reset) stop (stop) v dd v ss a maskable interrupt input pin of the edge trigger (rising edge). also, it can be used as a zero-cross detection pin for ac input. 8 pins of analog input to a/d converter. an7 to an4 can be used as edge detection (falling edge) input. a common pin serving both as a reference voltage input pin for a/d converter and as a control pin for a/d converter operation. power supply pin for a/d converter. gnd pin for a/d converter. crystal connection pins for system clock oscillation. x1 should be input when a clock is supplied from outside. inverted clock of x1 should be input in x2. low-level active system reset input. hardware stop mode control signal input pin. when the low level is input to this pin, the oscillation stops. positive power supply pin. gnd pin. pin name i/o function alternate function pin int1 (interrupt request) an7 to an0 (analog input) input input input v aref (reference voltage) av dd (analog v dd ) av ss (analog v ss ) input input 10 m pd78cp18(a) 1.3 non-port functions (during prom write/verify and read) pin name i/o function alternate function pin a7 to a0 input address lower 8 bit input pins chip enable signal input pin output enable signal input pin data input/output pins address higher 7 bit input pins set mode0 pin to 1 (high level), and mode1 pin to 0 (low level). set to 0 (low level). high-voltage application pin "1" (high level) is input when eprom is read. input ce input oe pb6 pb7 input/output o7 to o0 pd7 to pd0 input pf6 to pf2 a14 to a10 pa7 to pa0 pf0 a8 nmi a9 mode0 mode1 reset v pp input input input stop 1.4 handling of unused pins pa7 to pa0 pb7 to pb0 pc7 to pc0 pd7 to pd0 pf7 to pf0 rd wr ale stop int1, nmi av dd v aref av ss an7 to an0 recommended connection pin connect to v dd . connect to v ss or v dd . connect to v dd . connect to v ss . connect to av ss or av dd . leave open. connect to v ss or v dd via resistor. 11 m pd78cp18(a) 2. memory configuration the m pd78cp18(a) memory can operate in the following 4 modes according to the mode specification. l l m pd78c11a mode (see figure 2-1 ) l l m pd78c12a mode (see figure 2-2 ) l l m pd78c14 mode (see figure 2-3 ) l l m pd78c18 mode (see figure 2-4 ) in addition, the internal prom and internal ram address ranges can be specified for efficient mapping of external memory (excluding prom) (see 3.2 memory mapping register (mm) ). the vector area and call table area are common to all modes. setting the hardware/software stop mode or halt mode enables internal ram data to be retained at a low consumption current. 12 m pd78cp18(a) feffh ff00h ffffh 0080h 00bfh external memory 61184w 8 internal ram 256w 8 0000h 0000h 0004h reset nmi 0008h intt0/intt1 0010h int1/int2 0018h inte0/inte1 0020h intein/intad 0028h intsr/intst 0060h softi low adrs high adrs low adrs high adrs low adrs high adrs 0081h 0082h 0083h 00beh t = 0 t = 1 t = 31 call table area internal prom 4096w 8 0fffh 1000h 00c0h user's area 0fffh vector area figure 2-1. memory map ( m pd78c11a mode) 13 m pd78cp18(a) feffh ff00h ffffh 0080h 00bfh external memory 57088w 8 internal ram 256w 8 0000h 0000h 0004h reset nmi 0008h intt0/intt1 0010h int1/int2 0018h inte0/inte1 0020h intein/intad 0028h intsr/intst 0060h softi low adrs high adrs low adrs high adrs low adrs high adrs 0081h 0082h 0083h 00beh t = 0 t = 1 t = 31 call table area internal prom 8192w 8 1fffh 2000h 00c0h user's area 1fffh vector area figure 2-2. memory map ( m pd78c12a mode) 14 m pd78cp18(a) feffh ff00h ffffh 0080h 00bfh external memory 48896w 8 internal ram 256w 8 0000h 0000h 0004h reset nmi 0008h intt0/intt1 0010h int1/int2 0018h inte0/inte1 0020h intein/intad 0028h intsr/intst 0060h softi low adrs high adrs low adrs high adrs low adrs high adrs 0081h 0082h 0083h 00beh t = 0 t = 1 t = 31 call table area internal prom 16384w 8 3fffh 4000h 00c0h user's area 3fffh vector area figure 2-3. memory map ( m pd78c14 mode) 15 m pd78cp18(a) fbffh fc00h ffffh 0080h 00bfh external memory 31744w 8 internal ram 1024w 8 0000h 0000h 0004h reset nmi 0008h intt0/intt1 0010h int1/int2 0018h inte0/inte1 0020h intein/intad 0028h intsr/intst 0060h softi low adrs high adrs low adrs high adrs low adrs high adrs 0081h 0082h 0083h 00beh t = 0 t = 1 t = 31 call table area internal prom 32768w 8 7fffh 8000h 00c0h user's area 7fffh vector area figure 2-4. memory map ( m pd78c18 mode) 16 m pd78cp18(a) 3. memory extension the m pd78cp18(a) allows external memory extension by means of the memory mapping register (mm) or the mode0 and mode1 pins. also, the internal prom and internal ram access areas can be specified by means of bits mm7, mm6 and mm5 of the memory mapping register. 3.1 mode pins the m pd78cp18(a) can be switched between programming mode and normal operation mode according to the specification of the mode0 and mode1 pins. table 3-1 shows the modes set by the mode pins. table 3-1. modes set by mode pins mode1 mode2 operating mode l l setting prohibited l h programming mode note h l normal operation mode h h setting prohibited note see 4. prom programming . when mode0 and mode1 are driven high, a 4 [k w ] r 0.4 t cyc [k w ] pull-up resistor should be used (t cyc : ns units). 17 m pd78cp18(a) 3.2 memory mapping register (mm) the memory mapping register is an 8-bit register which performs the following controls: ? port/extension mode specification for pd7 to pd0 and pf7 to pf0 ? enabling/disabling of internal ram accesses ? specification of internal prom and ram access areas the configuration of the memory mapping register is shown in figure 3-1. (1) bits mm2 to mm0 these bits control the pd7 to pd0 port/extension mode specification, input/output specification, and the pf7 to pf0 address output specification. as shown in figure 3-1, there is a choice of four capacities for the connectable external memory: ? 256 bytes ? 4 kbytes ? 16 kbytes ? 32 k/48 k/56 k/60 kbytes (set by bits mm7 to mm5) ports of pf7 to pf0 not used as address outputs can be used as general-purpose ports. when reset signal is input or in the hardware stop mode, these bits are reset to (0) and pd7 to pd0 are set to input port mode (high-impedance). (2) mm3 bit (rae) this bit enables (rae = 1) and disables (rae = 0) internal ram access. this bit should be set to 0 during standby operation and when externally connected ram, not internal ram, is used. in normal operation this bit retains its value when reset signal is input. however, the rae bit is undefined after a power-on reset, and must therefore be initialized by an instruction. (3) bits mm7 to mm5 these bits specify the access area of the internal prom. when stop or reset signal is input, these bits are reset, selecting the 32-kbyte mode ( m pd78c18 mode). these bits are only valid in the m pd78cg14, 78cp14, 78cp18, 78cp14(a), and 78cp18(a); if data is written to these bits in the m pd78c11a(a), 78c12a(a), 78c14(a), or 78c18(a), it will be ignored. therefore, a program developed on the m pd78cp18(a) can be directly ported to mask rom. 18 m pd78cp18(a) figure 3-1. memory mapping register format 76543210 rae mm2 mm1 mm0 mm7 mm6 mm5 extension mode extension mode extension mode pd7 to pd0 = extension mode pf7 to pf0 = port mode pd7 to pd0 = input port pf7 to pf0 = port mode pd7 to pd0 = output port pf7 to pf0 = port mode pd7 to pd0 = pf3 to pf0 = pf7 to pf4 = port mode pd7 to pd0 = pf7 to pf0 = 32 k/48 k/ 56k/60k note bytes single chip port mode 256 bytes 4 kbytes exten- sion mode 16 kbytes 1 00 0 10 1 10 1 11 pd7 to pd0 = pf5 to pf0 = pf7 & pf6 = port mode 0 0 1 0 00 internal prom internal ram access area access area 0 0 0 0000h to 7fffh fc00h to ffffh (32 kbytes: (1 kbyte) m pd78c18 mode) 0 0 1 0000h to 3fffh ff00h to ffffh (16 kbytes: (256 bytes) m pd78c14 mode) 0 1 1 0000h to 1fffh ff00h to ffffh (8 kbytes: (256 bytes) m pd78c12a mode) 1 0 1 0000h to 0fffh ff00h to ffffh (4 kbytes: (256 bytes) m pd78c11a mode) other than above setting prohibited mm7 mm6 mm5 internal prom/ram access areas note depends on mm7 to mm5 bit-setting disable enable 0 1 internal ram access 19 m pd78cp18(a) figure 3-2. external extension modes set by memory mapping register caution the internal prom and internal ram access areas are determined by mm7 to mm5. external memory (32/48/56/ 60 kbytes) external memory (32/48/56/ 60 kbytes) internal prom (4/8/16/32 kbytes) not used 4-kbyte extension mode not used 256-byte extension mode not used port mode not used not used not used 64k internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal ram internal ram internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) internal prom (4/8/16/32 kbytes) external memory(256 bytes) external memory(256 bytes) external memory(256 bytes) internal ram internal ram internal ram internal ram internal ram internal ram external memory (16 kbytes) external memory (16 kbytes) external memory(4 kbytes) external memory(4 kbytes) internal ram internal ram 16-kbyte extension mode 32-/48-/56-/60-kbyte extension mode 00 64k 64k 0 64k 64k 0 0 20 m pd78cp18(a) pin name function reset low-level input (at write/verify and read) mode0 high-level input (at write/verify and read) mode1 low-level input (at write/verify and read) v pp note high-voltage input (at write/verify), high-level input (at read) ce note chip enable input oe note output enable input a14 to a0 note address input o7 to o0 note data input (at write), data output (at verify, read) v dd note supply voltage input 4. prom programming the m pd78cp18(a) incorporates 32768 8-bit prom as a program memory. the pins shown in table 4-1 are used for write/verify operations on this prom. m pd78cp18(a) program timing is compatible with the m pd27c256a. please read the following in conjunction with documentation of the m pd27c256a. table 4-1. pins used in prom programming note these pins correspond to the m pd27c256a. caution the m pd78cp18(a) one-time prom version is not equipped with an erasure window, and therefore ultraviolet erasure cannot be performed on it. 21 m pd78cp18(a) caution when +12.5 v is applied to v pp and +6 v is applied to v dd , setting both ce and oe to l is prohibited. table 4-3. recommended connection of unused pins (in prom programming mode) operating mode ce note oe note v pp note v dd note reset mode0 mode1 program l h +12.5 v +6 v l h l program verify h l program inhibit h h read l l +5 v +5 v output disable l h standby h l/h note these pins correspond to the m pd27c256a. 4.1 prom programming operating modes the prom programming operating mode is set as shown in table 4-2. pins not used for programming should be handled as shown in table 4-3. table 4-2. prom programming modes pin recommended connection int1 connect to v ss . x1 an0 to an7 v aref av dd av ss pins other than the connect to v ss via individual resistor. above x2 leave open. 22 m pd78cp18(a) a14/pf6-a10/pf2 a9/nmi a8/pf0 a7/pa7-a0/pa0 o7/pd7-o0/pd0 v pp v ih v dd + 1 v dd v ih v il v ih v il v pp v dd ce/pb6 oe/pb7 data input data output data input address (lower 8 bits) address (higher 7 bits) write verify additional write repeated x times 4.2 prom writing procedure the prom writing procedure is as shown below, allowing high-speed writing. (1) connect unused pins to v ss via a pull-down resistor, and supply +6 v to v dd and +12.5 v to v pp . (2) provide the initial address. (3) provide the write data. (4) provide a 1-ms program pulse (active low) to the ce pin. (5) verify mode. if written, go to (7); if not written, repeat (3) to (5). if the write operation has failed 25 times, go to (6). (6) halt write operation due to defective device. (7) provide write data and program pulse of x times x 3 ms (x; repeated times from (3) to (5)) (additional write). (8) increment the address. (9) repeat (3) to (8) until the final address. figure 4-1. prom write/verify timing 23 m pd78cp18(a) address input data output a14/pf6-a10/pf2 a9/nmi a8/pf0 ce/pb6 oe/pb7 o7/pd7-o0/pd0 4.3 prom reading procedure prom contents can be read onto the external data bus (o7 to o0) using the following procedure. (1) connect unused pins to v ss via a pull-down resistor. (2) supply +5 v to the v dd and v pp pins. (3) input address of data to be read to pins a14 to a0. (4) read mode (5) output data to pins o7 to o0. timing for steps (2) to (5) above is shown in figure 4-2. figure 4-2. prom read timing 24 m pd78cp18(a) 5. screening of one-time prom versions because of their construction, one-time prom versions cannot be fully tested by nec before shipment. after the necessary data has been written, it is recommended that screening be implemented in which prom verification is performed after high-temperature storage under the following conditions. storage temperature storage time 125 c 24 hours nec provides writing, marking, screening, and inspection services for single-chip microcomputers labeld qtop microcomputers. for details, consult nec. h 25 m pd78cp18(a) 6. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit v dd C0.5 to +7.0 v av dd av ss to v dd + 0.5 v power supply voltage av ss C0.5 to +0.5 v v pp C0.5 to +13.5 v other than nmi/a9 pin C0.5 to v dd + 0.5 v input voltage v i nmi/a9 pin C0.5 to +13.5 v output voltage v o C0.5 to v dd + 0.5 v all output pins 4.0 ma output current low i ol total of all output pins 100 ma all output pins C2.0 ma output current high i oh total of all output pins C50 ma a/d converter reference input voltage ambient operating temperature t a C40 to +85 c storage temperature t stg C65 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product with these rated values never exceeded. v aref C0.5 to av dd + 0.3 v h h 26 m pd78cp18(a) resonator recommended circuit parameter test conditions min. max. unit 415 ceramic or crystal oscillator frequency (f xx ) mhz resonator a/d converter used 5.8 15 a/d converter not used x1 input frequency (f x ) mhz external clock x1 rise time, fall time (t r , t f ) x1 input high-, low- level width (t f h , t f l ) cautions 1. place the oscillator as close as possible to the x1 and x2 pins. 2. ensure that no other signal lines pass through the shaded area. oscillator characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C0.8 v av dd v dd , 3.4 v v aref av dd ) x1 x2 c2 c1 x1 x2 hcmos inverter a/d converter used 5.8 15 a/d converter not used 020ns 20 250 ns 415 27 m pd78cp18(a) v il1 0 0.8 v parameter symbol test conditions min. typ. max. unit all except reset, stop, nmi, sck, int1, ti, an4 to an7 input voltage low reset, stop, nmi, sck, int1, ti, an4 to an7 all except reset, stop, nmi, sck, int1, ti, an4 to an7, x1, x2 input voltage high reset, stop, nmi, sck, int1, ti, an4 to an7, x1, x2 output voltage low v ol i ol = 2.0 ma 0.45 v v dd C 1.0 output voltage high v oh v dd C 0.5 input current i i int1 note1 , ti(pc3) note2 ; 0 v v i v dd 200 m a all except int1, ti (pc3), input leakage an7 to an0; 0 v v i v dd current an7 to an0; 0 v v i v dd 1 m a output leakage current ai dd1 operating mode f xx = 15 mhz 0.5 1.3 ma ai dd2 stop mode 10 20 m a i dd1 operating mode f xx = 15 mhz 16 35 ma i dd2 halt mode f xx = 15 mhz 7 13 ma data retention voltage hardware/software note3 v dddr = 2.5 v 1 15 m a i dddr stop mode v dddr = 5 v 10 % 10 50 m a dc characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i 10 pf f c = 1 mhz output capacitance c o unmeasured pins 20 pf returned to 0 v input-output capacitance c io 20 pf capacitance (t a = 25 c, v dd = v ss = 0 v) notes 1. if self-bias should be generated by zcm register. 2. if the control mode is set by mcc register, and self-bias should be generated by zcm register. 3. if self-bias is not generated. v il2 0 0.2v dd v v ih1 2.2 v dd v v ih2 0.8 v dd v dd v 10 m a i lo 0 v v o v dd 10 m a i li av dd power supply current v dd power supply current data retention current v dddr hardware/software stop mode 2.5 v i oh = C1.0 ma v i oh = C100 m a v h 28 m pd78cp18(a) ac characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) read/write operation: parameter symbol test conditions min. max. unit x1 input cycle time t cyc 66 167 ns address setup time (to ale ? )t al 30 ns address hold time (from ale ? )t la f xx = 15 mhz, cl = 150 pf 35 ns rd ? delay time from address t ar 100 ns address float time from rd ? t afr c l = 150 pf 20 ns data input time from address t ad 250 ns data input time from ale ? t ldr 135 ns f xx = 15 mhz, c l = 150 pf data input time from rd ? t rd 120 ns rd ? delay time from ale ? t lr 15 ns data hold time (from rd )t rdh c l = 150 pf 0 ns ale delay time from rd t rl f xx = 15 mhz, c l = 150 pf 80 ns in data read f xx = 15 mhz, c l = 150 pf rd low-level width t rr in op code fetch f xx = 15 mhz, c l = 150 pf ale high-level width t ll f xx = 15 mhz, c l = 150 pf 90 ns wr ? delay time from address t aw 100 ns f xx = 15 mhz, c l = 150 pf data output time from ale ? t ldw 197 ns data output time from wr ? t wd c l = 150 pf 140 ns wr ? delay time from ale ? t lw 15 ns data setup time (to wr )t dw 127 ns data hold time (from wr )t wdh f xx = 15 mhz, c l = 150 pf 60 ns ale delay time from wr t wl 80 ns wr low-level width t ww 215 ns 215 ns 415 ns parameter symbol test conditions min. max. unit zero-cross detection input v zx 1 1.8 vac p-p zero-cross accuracy a zx ac coupling 135 mv 60-hz sine wave zero-cross detection input frequency zero-cross characteristics : f zx 0.05 1 khz 29 m pd78cp18(a) parameter symbol test conditions min. max. unit note1 800 ns sck input sck cycle time t cyk note2 400 ns sck output 1.6 m s note1 335 ns sck input sck low-level width t kkl note2 160 ns sck output 700 ns note1 335 ns sck input sck high-level width t kkh note2 160 ns sck output 700 ns r x d setup time (to sck )t rxk note1 80 ns r x d hold time (from sck )t krx note1 80 ns t x d delay time from sck ? t ktx note1 210 ns notes 1. if clock rate is 1 in asynchronous mode, synchronous mode, or i/o interface mode. 2. if clock rate is 16 or 64 in asynchronous mode. remark the numeric values in the table are those when f xx = 15 mhz, cl = 100 pf. serial operation : other operation : parameter symbol test conditions min. max. unit ti high-, low-level width t tih , t til 6t cyc ? event counter mode t ci1h , t ci1l 6t cyc ? frequency test mode ci high-, low-level width ? pulse width test mode t ci2h , t ci2l ? ecnt latch and clear input 48 t cyc ? intein set input nmi high-, low-level width t nih , t nil 10 m s int1 high-, low-level width t i1h , t i1l 36 t cyc int2 high-, low-level width t i2h , t i2l 36 t cyc an4 to an7, low-level width t anh , t anl 36 t cyc reset high-, low-level width t rsh , t rsl 10 m s 30 m pd78cp18(a) 2.2 v 0.8 v 2.2 v 0.8 v test points v dd ?1.0 v 0.45 v a/d converter characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd , 3.4 v v aref av dd ) parameter symbol test conditions min. typ. max. unit resolution 8 bits 3.4 v v aref av dd , 66 ns t cyc 167 ns 0.8 % fsr absolute accuracy note 4.0 v v aref av dd , 66 ns t cyc 167 ns 0.6 % fsr t a = C10 to +70 c, 4.0 v v aref av dd , 66 ns t cyc 167 ns 66 ns t cyc 110 ns 576 t cyc conversion time t conv 110 ns t cyc 167 ns 432 t cyc 66 ns t cyc 110 ns 96 t cyc sampling time t samp 110 ns t cyc 167 ns 72 t cyc analog input voltage v ian C0.3 v aref + 0.3 v analog input impedance reference voltage v aref 3.4 av dd v i aref1 operating mode 1.5 3.0 ma v aref current i aref2 stop mode 0.7 1.5 ma av dd power supply ai dd1 operating mode f xx = 15 mhz 0.5 1.3 ma current ai dd2 stop mode 10 20 m a note quantization error ( 1/2 lsb) is not included. ac timing test point r an 50 m w 0.4 % fsr h 31 m pd78cp18(a) parameter expression min./max. unit t al 2t C 100 min. ns t la t C 30 min. ns t ar 3t C 100 min. ns t ad 7t C 220 max. ns t ldr 5t C 200 max. ns t rd 4t C 150 max. ns t lr t C 50 min. ns t rl 2t C 50 min. ns 4t C 50 (in data read) t rr min. ns 7t C 50 (in op code fetch) t ll 2t C 40 min. ns t aw 3t C 100 min. ns t ldw t + 130 max. ns t lw t C 50 min. ns t dw 4t C 140 min. ns t wdh 2t C 70 min. ns t wl 2t C 50 min. ns t ww 4t C 50 min. ns 12t (sck input) note1 t cyk 6t (sck input) note2 min. ns 24t (sck output) 5t + 5 (sck input) note1 t kkl 2.5t + 5 (sck input) note2 min. ns 12t C 100 (sck output) 5t + 5 (sck input) note1 t kkh 2.5t + 5 (sck input) note2 min. ns 12t C 100 (sck output) notes 1. if clock rate is 1, in asynchronous mode, synchronous mode, or i/o interface mode. 2. if clock rate is 16, 64 in asynchronous mode. remarks 1. t = t cyc = 1/f xx 2. other items which are not listed in this table are not dependent on oscillator frequency (f xx ). t cyc -dependent ac characteristics expression 32 m pd78cp18(a) x1 pf7 to pf0 pd7 to pd0 ale t cyc address (higher) address (lower) t rdh read data t ldr t ad t rl t rd t rr t afr t la t ll t ar t al t lr rd address (higher) address (lower) t ldw t ll t al t wd t dw t wdh t wl t ww t lw t aw write data x1 pf7 to pf0 pd7 to pd0 ale wr t la timing waveforms read operation write operation 33 m pd78cp18(a) serial operation timer/event counter input timing timer input timing t cyk t kkl t kkh t rxk t krx t ktx sck t x d r x d ti t til t tih ci t ci1l t ci1h event counter mode ci t ci2l t ci2h pulse width test mode 34 m pd78cp18(a) x1 t cyc t f h 0.8v dd 0.8 v t f t r t f l reset t rsl t rsh 0.8v dd 0.2v dd interrupt input timing external clock timing reset input timing nmi t nil t nih int1 int2 t i1h t i1l t i2l t i2h 35 m pd78cp18(a) 90 % stop v dd v dddr t rvd 10 % t fvd t sstvd t hvdst v ih2 v il2 parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr = 2.5 v 1 15 m a i dddr v dddr = 5 v 10 % 10 50 m a v dd rise/fall time t rvd , t fvd 200 m s stop setup time t sstvd 12t + 0.5 m s (to v dd ) note stop hold time t hvdst 12t + 0.5 m s (from v dd ) note data memory stop mode low power supply voltage data retention characteristics (t a = C40 to +85 c) note t= t cyc = 1/f xx data retention timing v dddr 2.5 5.5 v h supply current data retention power 36 m pd78cp18(a) 550 ma 530 ma input voltage high v ih v ih 2.4 v parameter symbol symbol note test conditions min. typ. max. unit v ddp + 0.3 input voltage low v il v il C0.3 0.8 v input leakage current i lip i li 0 v i v ddp ; except int1, ti (pc3) 10 m a v dd C 1.0 output voltage low v ol v ol i ol = 2.0 ma 0.45 v output leakage current eprom programming mode 5.75 6.0 6.25 v eprom read mode 4.5 5.0 5.5 v eprom programming mode 12.2 12.5 12.8 v eprom read mode v pp = v ddp v eprom programming mode 5 50 ma eprom read mode ce = v il , v i = v ih eprom programming mode ce = v il , oe = v ih eprom read mode 1 100 m a dc programming characteristics (t a = 25 5 c, mode1 = v il , mode0 = v ih , v ss = 0 v) note corresponding m pd27c256a symbol output voltage high v oh v oh i oh = C1.0 ma v v ddp supply voltage v ddp v dd v pp supply voltage v pp v pp v ddp supply current i dd i dd v pp supply current i pp i pp i lo CC 0 v o v ddp , oe = v ih 10 m a 37 m pd78cp18(a) t smc CC 2 m s ac programming characteristics (t a = 25 5 c, mode1 = v il , mode0 = v ih , v ss = 0 v) parameter symbol symbol note1 test conditions min. typ. max. unit address setup time (to ce ? )t sac t as 2 m s oe ? delay time from data t ddoo t oes 2 m s input data setup time (to ce ? )t sidc t ds 2 m s address hold time (from ce )t hca t ah 2 m s input data hold time (from ce )t hcid t dh 2 m s output data hold time (from oe )t hood t df 0 130 ns v pp setup time (to ce ? )t svpc t vps 2 m s v ddp setup time (to ce ? )t svdc t vds 2 m s initial program pulse width t wl1 t pw 0.95 1.0 1.05 ms additional program pulse width t wl2 t opw 2.85 78.75 ms eprom programming/read mode setup time (to ce ? ) note2 data output time from address t daod t acc oe = v il 1 m s data output time from ce ? t dcod t ce 1 m s data output time from oe ? t dood t oe 1 m s data hold time (from oe )t hcod t df 0 130 ns data hold time (from address) t haod t oh oe = v il 0ns notes 1. corresponding m pd27c256a symbol 2. indicates state in which mode1 = v il and mode0 = v ih . 38 m pd78cp18(a) a12 to a0 effective address data output hi-z ce oe d7 to d0 t dcod t daod t dood hi-z t hcod t haod a12 to a0 effective address d7 to d0 data input data output data input v pp v ddp v ddp + 1 v ddp v ih v il v ih v il v pp v ddp ce oe v ih v il mode1 mode0 mode1 = v il mode0 = v ih t sac t sidc t smc t svpc t svdc t hcid t hood t hca t sidc t hcid t wl2 t wl1 t ddoo t dood prom programming mode timing cautions 1. ensure that v ddp is applied before v pp , and cut after v pp . 2. ensure that v pp does not exceed +13 v including overshoot. prom read mode timing cautions 1. if you wish to read within the t daod range, the oe input delay time from the fall of ce should be a maximum of t daod - t dood . 2. t hcod is the time from the point at which oe or ce (whichever is first) reaches v ih . 39 m pd78cp18(a) 30 25 20 15 10 5 0 0 4.5 5.0 5.5 (t a = 25 ?c, f xx = 15 mhz) i dd1 (typ.) power supply voltage v dd [v] v dd power supply current i dd1 , i dd2 [ma] (t a = 25 ?c, v dd = 5 v) oscillator fre q uenc y f xx [mhz] v dd power supply current i dd1 , i dd2 [ma] 30 20 10 0 0 5 10 15 i dd1 (typ.) i dd2 (typ.) i dd2 (typ.) 6.0 7. characteristic curves (reference value) i dd1 , i dd2 vs. v dd i dd1 , i dd2 vs. f xx 40 m pd78cp18(a) i ol vs. v ol i oh vs. v oh 2.5 2.0 1.5 1.0 0.5 0 0 0.1 0.2 0.3 0.4 0.5 (t a = 25 ?c, v dd = 5 v) typ. output voltage low v ol [v] output current low i ol [ma] ?.5 ?.0 ?.5 0 0 0.1 0.2 0.3 0.4 0.5 (t a = 25 ?c, v dd = 5 v) power supply voltage ?output voltage high v dd ?v oh [v] output current high i oh [ma] typ. 41 m pd78cp18(a) i dddr vs. v dddr 10 8 6 4 2 0 0 23456 (t a = 25 ?c) typ. data retention power supply voltage v dddr [v] data retention power supply current i dddr [ a] m 42 m pd78cp18(a) 8. package drawings h i m c p a 64 132 33 m n j k s w x p64gq-100-36 item millimeters inches a c h i j k m n p s w 1.27 (t.p.) 0.25 16.5 0.100 (t.p.) 0.050 (t.p.) 0.010 0.157 1.634 note x 4.0 0.750 each lead centerline is located within 0.25 mm (0.010 inch) of its true position (t.p.) at maxi- mum material condition. 0.142 0.043 0.020 24.13 0.950 0.010 0.25 2.54 (t.p.) +0.004 ?.005 +0.011 ?.006 +0.012 ?.008 +0.004 ?.005 41.5 +0.3 ?.2 0.50 +0.10 1.1 +0.25 ?.15 +0.10 ?.05 +0.3 3.6 +0.1 +1.05 19.05 +1.05 0.650 +0.004 ?.003 +0.013 ?.012 +0.042 +0.042 64 pin plastic quip 43 m pd78cp18(a) n a m f b 51 52 32 k l 64 pin plastic qfp (14 20) 64 1 20 19 33 p d c detail of lead end s q 55 g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 44 m pd78cp18(a) infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or higher), ir35-00-2 count: twice or less 45 m pd78cp18(a) internal rom 32 k 8 bits 32 k 8 bits (prom) (mask rom) internal ram 1 k 8 bits 1 k 8 bits pin connection pb7/oe pb7 pb6/ce pb6 stop/v pp stop nmi/a9 nmi pa7/a7 to pa0/a0 pa7 to pa0 pf6/a14 to pf2/a10 pf6 to pf2 pf0/a8 pf0 pd7/o7 to pd0/o0 pd7 to pd0 mode set by mode pins (when prom programming mode ? operates as the m pd78c17(a) mode0 is set to 1, and mode1 (rom-less mode) to 0) ? external memory 16 k extension mode mode0 pin input/output function input only note input/output internal memory access area yes no setting by mm register port a to port c pull-up resistors not incorporated pull-up resistor incorporation selectable bit-wise by mask option note an emulation control signal is not output even if the mode0 pin is pulled high. 10. differences between the m pd78cp18(a) and m pd78c18(a) m pd78cp18(a) m pd78c18(a) part number item 46 m pd78cp18(a) ordering code (product name) m s5a13ra87 m s5a10ra87 m s7b13ra87 m s7b10ra87 appendix development tools the following development tools are available to develop a system which uses the m pd78cp18(a). language processor this is a program which converts a program written in mnemonic to an object code for which microcomputer execution is possible. moreover, it contains a function to automatically create a symbol/table, and optimize branch instructions. 87ad series relocatable assembler (ra87) supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc h pg-1500 pa-78cp14gf/ gq pa-78cp14gf pa-78cp14gq pg-1500 controller prom write tools with a provided board and an optional programmer adapter connected, this prom programmer can manipulate from a stand-alone or host machine to perform programming on a single-chip microcomputer which incorporates prom. it is also capable of programming a typical prom ranging from 256 k to 4 m bits. prom programmer adapter for the m pd78cp18(a). used by connecting to the pg-1500. for the m pd78cp18gf(a)-3be for the m pd78cp18gq(a)-36 connects the pg-1500 to a host machine by using serial and parallel interface, to control the pg- 1500 on a host machine. hardware ordering code (product name) m s5a13pg1500 m s5a10pg1500 m s7b10pg1500 supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc host machine pc-9800 series ibm pc/at software note versions 5.00 and 5.00a have a task swap function, but this function cannot be used with this software. remark the operations of the assembler and the pg-1500 controller are guaranteed only on the above host machines and operating systems. os ms-dos ver. 2.11 to ver. 5.00a note pc dos (ver. 3.1) os ms-dos tm ver. 2.11 to ver. 5.00a note pc dos tm (ver. 3.1) host machine pc-9800 series ibm pc/at tm 47 m pd78cp18(a) debugging tools an in-circuit emulator (ie-78c11-m) is available as a program debugging tool for the m pd78cp18(a). the following table shows its system configuration. remark the operations of the ie controller are guaranteed only on the above host machines and operating systems. ie-78c11-m ie-78c11-m control program (ie controller) the ie-78c11-m is an in-circuit emulator which works with the 87ad series. it can be connected to a host machine to perform efficient debugging. connects the ie-78c11-m to host machine by using the rs-233c, to control the ie-78c11-m on host machine. hardware ordering code (product name) m s5a13ie78c11 m s5a10ie78c11 m s7b10ie78c11 supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc host machine pc-9800 series ibm pc/at os ms-dos ver. 2.11 to ver. 3.30d pc dos (ver. 3.1) software 48 m pd78cp18(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards wiht semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd78cp18(a) qtop is a trademark of nec corporation. ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 [memo] |
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